发明名称 RESETTING CIRCUIT
摘要 PURPOSE:To eliminate malfunction due to differences in threshold voltage and operating voltage, and control a resetting circuit even by the stop of a clock signal by generating a control signal through AND operation between the output of a source voltage drop detecting circuit and an external clock. CONSTITUTION:An AND gate 24 outputs the clock signal when the output of the source voltage drop detecting circuit 9 decreases below the threshold voltage. A counter 26 outputs a unit step signal a set time of T seconds later to a monostable multivibrator 27 by said clock signal, and the monostable multivibrator 27 outputs one pulse, An FF28 receives it and its output Q resets the reset R of a multivibrator 29. The multivibrator 29 sends out a specific output signal when input pulse width is larger than pulse width set by the multivibrator 29 by the clock signal outputted by the AND gate 24. Then, a microprocessor 23 decreases the output to a low level when necessary. Namely, the counter 26 is controlled by the AND gate 24, so malfunction due to power source variation is prevented.
申请公布号 JPS59212025(A) 申请公布日期 1984.11.30
申请号 JP19830086917 申请日期 1983.05.18
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SATOU HIDETO;MOGI KOUSEI
分类号 H03K21/38;H03K17/22 主分类号 H03K21/38
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