发明名称 FAULT SUPERVISING CIRCUIT
摘要 PURPOSE:To measure the duration time of plural fault information by one counter circuit by applying time division and multiplex at each unit to the plural fault information then multiplexing the resulted information in time series, and sampling the duration time of said information having an fault at each specific period. CONSTITUTION:Pieces of fault information a1-al detected by units U1-Un are multiplexed by a multiplexing circuit 5 in each unit. The wired-OR constitution is adopted by using a tri-state buffer 6 in order to apply multiplication further. A supervising section SV consists of a counter circuit 7, a memory circuit 9 and a flip-flop circuit 8 or the like. The counter circuit 7 inputs duration time information read by a memory circuit 9 based on input fault information 6-1, stores this output information at a flip-flop circuit 8 and inputs it to the memory circuit 9. Then, the duration time at each fault type is counted by one counter circuit 7 by using the counter circuit in terms of time division.
申请公布号 JPS59211342(A) 申请公布日期 1984.11.30
申请号 JP19830085265 申请日期 1983.05.16
申请人 NIPPON DENKI KK 发明人 TSUTSUI KOUJI
分类号 H04B17/00 主分类号 H04B17/00
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