发明名称 PHASE-LOCKED LOOP CIRCUIT DEVICE
摘要 PURPOSE:To prevent the unlocking of a PLL because of application of power or other external disturbances by detecting the unlocking of the phase-locked loop or the state in the vicinity of the unlocking based on a control voltage applied to a voltage controlled oscillator from a low-pass filter and controlling the control voltage so as to be led within the locking range. CONSTITUTION:When the PLL circuit is operated normally, since an output voltage of the 1st voltage comparator 13 is kept to a low level Vcc1(-) and an output voltage of the 2nd voltage comparator 14 is kept to a high level Vcc2 (+), diodes 25, 26 as selective current supply circuits are kept both turned off. If the control voltage Vc exceeds a lock range upper limit voltage V4 because of power application or other external disturbance or the like, the output voltage of the 1st voltage comparator 13 reaches the high level voltage Vcc1(+), the diode 25 is turned on and the control voltage Vc of the output stage of an operational amplifier 7 is decreased. If the control voltage Vc is decreased less than a lock range lower limit voltage V1 due to any cause, the output voltage of the 2nd voltage comparator 14 is inverted into the low level voltage Vcc2 (-), the diode 26 is turned on, a negative voltage is applied to the low-pass filter 2, causing a current to be extracted from the low-pass filter 2 through a resistor 27.
申请公布号 JPS59210731(A) 申请公布日期 1984.11.29
申请号 JP19830083766 申请日期 1983.05.13
申请人 IWASAKI TSUSHINKI KK 发明人 TANAKA KATSUAKI
分类号 H03L7/10;(IPC1-7):H03L7/10 主分类号 H03L7/10
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