| 摘要 |
PURPOSE:To attain the speed conversion via a selection circuit and the 2nd shift register by providing the selection circuit to the 1st shift register to feed the data obtained by shifting the input data to the 2nd shift register. CONSTITUTION:The input data (a) is successively supplied to a shift register 7 by a clock (g). The input of a selection circuit 6 is switched to B by a selection input (h) as soon as the input of data (a) is through. Then the output of the register 7 is applied to an input terminal D of each flip-flop of a shift register circuit 5. At the same time, the output of the circuit 7 is delivered to an output terminal Q of each flip-flop with another clock (i). Then the input of the circuit 6 is switched to A by the input (h), and the circuit 5 is reset to the original shift register state. The input data is successively shifted by the input clock (i) and sent to the outside in the form of output data (d). |
