| 摘要 |
PURPOSE:To make the scale of an additional circuit small and facilitate the test of bit error correcting operation for a memory cell by using a data inputting circuit of initial setting and a data control circuit for test in common with a writing control circuit to a memory cell and inspection cell. CONSTITUTION:When a control signal given to a control terminal EC is ''O'', input data from an input terminal DI are transmitted as they are to all of reading buses BMI, BHI, BVI at the time of writing and initial setting is made possible. When the control signal given to a control terminal EC is ''I'', input data from the input terminal DI are transmitted to a writing bus BMI at the time of writing. Updated data are transmitted to writing buses BHI, BVI basing on the result of comparison of input data and memory cell information before writing so that horizontal parity and vertical parity obtain even number parity. That is, self correcting type memory can be realized by performing ordinary random access. |
