| 摘要 |
PURPOSE:To reduce an area while also lowering the resistance of an address line by wiring one layer section of an output line with a conductive metal, wiring the address line with polycrystalline Si and the conductive metal of a second layer section and connecting polycrystalline Si and the metal of the second layer section at every predetermined bit section in an ROM in which a plurality of transistors are connected in parallel between at least one output line and at least one reference potential line. CONSTITUTION:Address lines in an ROM are wired by polycrystalline Si and Al of a second layer section, and these polycrystalline Si and Al are connected at regular intervals to lower the resistance of the address lines. That is, the ROM is constituted by digit wirings 1 consisting of Al wirings of a first layer section, a polycrystalline Si wiring 2 combining address wirings and gate electrodes, an Al wiring 3 for the second layer section for the address wirings, a diffusion layer 4, contact holes 5 for connecting the wirings 2 and 1, and through-holes 6 for connecting the wirings 1 and 3. Accordingly, the connecting area of the wirings 2 and 3 is reduced, and the speed of the ROM is increased. |
