发明名称 TEST SYSTEM OF INPUT AND OUTPUT DEVICE
摘要 PURPOSE:To perform a test in consideration of the margin of an input/output device by using an interface adaptor which works by an instruction given from a controller. CONSTITUTION:A controller 1 transmits the address of an interface adaptor 2. A selection/instruction analysis circuit 4 confirms the coincidence of addresses and analyzes and stores the instructions which are given sequentially. When the end of this storage is reported to the controller 1, the controller 1 proceeds to the selection sequence of an input/output device 3 and transmits the address and test signal. An interface searching circuit 6 detects the break point of said test signal from the signals supplied through terminals A and C and produces the trigger signal. This trigger signal is applied to an error generating circuit 5, and the circuit 5 superposes noises and produces signal cracks to vary the test signal. This vaired test signal is sent to the device 3. This result is sent to the controller 1 from the terminal C via a terminal D, and the controller 1 decides the result.
申请公布号 JPS59211118(A) 申请公布日期 1984.11.29
申请号 JP19830085311 申请日期 1983.05.16
申请人 FUJITSU KK 发明人 TSUCHIYA HIDEAKI
分类号 G06F3/06;G06F3/00;G06F13/00;H04L29/14 主分类号 G06F3/06
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