| 摘要 |
<p>A method for manufacturing a gate array IC device in which the turn-around time of a design is short, the system design is simple, and the fast-access memory capacity required in the design process is reduced. The method includes manufacturing a master bulk pattern of a basic cell array on the semiconductor substrate, and storing, in semi-permanent memory, symbol data and detailed data for standard macro cells and standard expandes macro cells prior to designing a logic system. Each macro cell comprises one or more basic cells and has a basic logic function. Each expanded macro cell comprises plural macro cells and has a more complicated and sophisticated logic function than the macro cells. In addition, the logic functions of the expanded macro cells are standard in the logic system design technology area. When a designer creates a logic system, only symbol data for macro cells (DO, EO,...) and the expanded macro cells (500) are the connections thereof (111, 112,...) are used and stored in the memory, so that it is relatively easy to design the system. Actual conductive wiring patterns are synthesized from the logic system data and the detailed data; these patterns are produced on the semiconductor substrate which is already provided with a master bulk pattern so as to connect the basic cells in accordance with the design.</p> |
