| 摘要 |
This invention is a data line interface providing a parallel to serial conversion technique for selectively increasing serial data transmission rates. The data line interface receives a 16-bit data word or signal from a TDM bus and transmits it serially to one of a plurality of data terminal interfaces depending on which one is selected. The invention utilizes a double buffer receiver circuit to determine when to speed up the destination transmission clock. The asynchronous data line interface looks at the value of each of the bits in the data word by sampling the center of each bit. However, during the stop bit, it will not look at the value after sampling the center. Thus, during the time that would have been devoted to the last half of the stop bit, a new start bit may be accepted, allowing the speed up of data to occur.
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