发明名称 FILTER CIRCUIT
摘要 PURPOSE:To eliminate clock leakage and to attain signal transmission free from noise by using a sampling/holding circuit which works on a switch signal having a frequency of (n) times as high as the switching frequency which drives a switched capacitor filter to eliminate the noise component of said filter. CONSTITUTION:A noise component produced by the clock leakage is superposed on an output signal Vout, and this noise component is generated in response to the switching frequency of a 1/2 frequency dividing circuit 2i. Here the switching signal fO supplied to a sampling/holding circuit 3 corresponds to switching frequencies phi and -phi obtained from the circuit 2i. In other words, these frequencies phi and -phi are obtained by giving successively 1/2 division to the signal fO. As a result, the noise components superposed on the signal Vout are all eliminated through the circuit 3. Therefore, no noise component emerges at all to an output signal Vout' which is obtained from the circuit 3.
申请公布号 JPS59208922(A) 申请公布日期 1984.11.27
申请号 JP19830082653 申请日期 1983.05.13
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU TETSUO;WATANABE TOSHIHIKO
分类号 H03H19/00;(IPC1-7):H03H19/00 主分类号 H03H19/00
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