| 摘要 |
PURPOSE:To enable to obtain a low resistance wiring layer by a method wherein a high melting point metal silicide layer is covered on a shallow impurity diffusion layer and a thin poly Si layer. CONSTITUTION:An N-well region 404 and a field oxide film 405 are formed on a P type single crystal Si substrate 401. Then, a gate insulating film 406 is formed on the surface of the substrate 401 of an active region. Subsequently, an aperture is provided on the film 406 located on the region where a direct contact will be formed, and after an Si face has been exposed, poly Si is coated, and a gate electrode 407g and an output wiring 407c are formed by doping N type and P type impurities respectively. Then, the film 406 is removed using a poly Si pattern as a mask. Then, after an Mo film 410 has been coated on the whole surface, an N type doped layer 408 is formed by implanting N type impurities, and a P type doped layer 409 is formed by implanting P type impurities and Si. The interface where Mo comes in contact with Si is mixed by the above-mentioned implantation. Then, a smooth and uniform Mo silicide 411 is formed by performing a heat treatment at 400-600 deg.C in hydrogen gas. Subsequently, non-reacted Mo is removed, and a heat treatment is performed at 800 deg.C or above in nitrogen gas. |
