| 摘要 |
<p>A communication link has a memory unit including a common section accessable to all ports of the link and several local sections each associated with one of the ports and accessable to its associated port, and no other port. A dual memory bus with a common bus subsystem provides access to the common mem-ory section and a local bus subsystem provides access to the local memory sections. The common and local subsystems are constructed to enable concurrent independent use. The ports include decoding circuitry which receives signals from its associated station and in response thereto emits signals distinctively indicating the need for access to common or local memory, which emitted signals are transmitted to memory priority circuitry supplying timed signals which designate for each memory operating cycle the one of the ports which may have access to the memory. Access is made available to the several ports in cyclic order. The memory priority circuitry also designates for each memory cycle one of the ports for current service and responds to request signals from elements of the link indicating needs for memory access, and if the currently designated port requests memory access, the memory priority circuitry enables the currently designated port to use the common bus subsystem or the local memory bus subsystem in accordance with the signaled needs of the currently designated port, while concurrently enabling other elements of the link to use the bus subsystems not requested by the currently designated port.</p> |
