| 摘要 |
PURPOSE:To attain carefull fault control of an address array by providing the titled device with a tag storage device, a comparator and a detector, and when an error is detected at the address array, operating the address array continuously. CONSTITUTION:Address information at the time of main storage reading/writing which is sent from a processor 1 through a main storage address information line 11 and a main storage address redundant bit information line 12 is set up in a register 2. Plural address data and address reduntant bit information read out from a tag storage device 3 are sent to the comparator 4 and the detector 5 respectively. When an incorrect position display signal is generated on a signal line 20, a block load control device 9 starts the same processing as a normal miss bit. On the other hand, an invalidation indicating signal is sent from an invalidation processor 6 to the tag storage device 3 through a signal line 21 and the corresponding block of the tag storage device 3 is invalidated. |
