发明名称 INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce the size of a chip, by constituting a power feeding pattern by main line patterns extended from a bus line pattern into wiring regions between blocks and branch patterns extended to block feeding points from the main line patterns. CONSTITUTION:On a semiconductor chip 10 formed in a rectangular shape, blocks 14-1-14-9 are arranged. A rectangular bus line pattern 16 is formed so as to surround the blocks 14-1-14-9. The blocks 14-1 is constituted by cells 12-1 and 12-2. The other blocks 14-2-14-9 are similarly constituted. Power distributing patterns 18-1 and 18-2 of each block are not formed to be extended out of the region of the block but formed to power feeding points 22-1-22-4 at block- boundary positions. Therefore, even though blocks having different sizes are arranged depending on the functions, the layout of the blocks can be optimized and the chip size can be reduced.
申请公布号 JPS59207641(A) 申请公布日期 1984.11.24
申请号 JP19830080839 申请日期 1983.05.11
申请人 HITACHI SEISAKUSHO KK 发明人 YAMAKAMI TOSHIYUKI
分类号 H01L21/822;G11C11/401;H01L21/82;H01L27/02;H01L27/04 主分类号 H01L21/822
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