| 摘要 |
PURPOSE:To decrease the number of address pins as well as the access time by providing an address buffer which receives the address of a Z system in addition to an XY system and a circuit having the function of a Z address decoder. CONSTITUTION:A memory array 1 selects a memory cell of plural bits which receives accesses from X and Y decoder circuits 2 and 3. A latch circuit 6 holds the data of plural bits. A gate means 7 transmits the data held at the circuit 6 selected by a Z decoder circuit 8 or the data supplied from outside for each bit. A control circuit 5 controls these circuits. The decoder circuits 2, 3 and 8 are actuated successively by the address signal supplied from outside via the same terminal group. Thus the desired data is read out of a memory array 1 or written to the array 1. |
