| 摘要 |
The invention relates to an elementary binary adder with a particularly regular and compact structure, having identical propagation times for the sum and the carry and having low consumption. It comprises inputs A and B for two signals a and b to be added, an input C for a carry c, inverters Ia, Ib, Ic at the output of each input, two routing switches AIG1 and AIG2 controlled by the input signals a and b and their complements; the first routing switch AIG1 receives, as signals to be routed, the carry and its complement and delivers the sum S of the addition. The second routing switch AIG2 receives as signals to be routed the complement of the carry, a logic level 0 and a logic level 1; it supplies the carry R of the addition. Application to networks of adders in a multiplier. <IMAGE>
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