发明名称 DATA PROCESSING SYSTEM
摘要 PURPOSE:To perform the direct memory access (DMA) to a storage device having large capacity with an input-output control device prepared correspondingly to a storage device of small capacity, by installing an address for holding an extended address bit to a CPU. CONSTITUTION:A storage device 2, CPU1, and input-output devices 3-0-3-3 are connected with a common bus 5. The storage device 2 has capacity of, for example, 256 KB and the address bit line of the CPU 1 and common bus 5 is constituted with 18 bits correspondingly to the 256 KB. When only the input-output control device 3-3 is constituted with 18-bit address line and the other devices 3-0-3-2 are constituted with 16-bit address lines and can correspond to 64 KB only, registers 6-0-6-3 in the CPU 1 are installed correspondingly to the input- output control devices 3-0-3-3 and a 2-bit capacity is provided to each register 6-0-6-3. When such an arrangement is made, the input-output control devices can be used efficiently, because even from the input-output control device 3-0- 3-2 DMA to the CPU 1 having the large capacity can be made.
申请公布号 JPS59206925(A) 申请公布日期 1984.11.22
申请号 JP19830081338 申请日期 1983.05.10
申请人 PANA FACOM KK 发明人 NAKA KENICHI;IINUMA HIROSHI
分类号 G06F13/28;G06F3/00 主分类号 G06F13/28
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