| 摘要 |
PURPOSE:To attain diagnosis using a logical part formed for scanning by adding a data entering function to be operated independently of a logical clock to latches specifying a diagnosis address. CONSTITUTION:OR gates 14, 14' and AND gates 15, 15' are respectively incorporated in the prestages of clocks 9, 9' of the latches provided with scanning circuits. The gates 15, 15' find AND between scanning addresses of respective latches and a common clock terminal 16 for diagnosis and the gates 14, 14' find OR between the outputs of the gates 15, 15' and a clock to be used for logic. To diagnize a combining circuit part 10, all logical clock inputs and the terminal 16 are turned to the low levels, the latches are turned to the holding state, the input side latch 4 is initialized, and after initialization, a scanning address is set up in the output side latch 11. After the setting, the terminal 16 is turned to the high level and data are inputted and read out from a scanning out terminal 13 to execute the diagnosis. |
