| 摘要 |
<p>A monolithically integrable circuit arrangement includes a memory with non-volatile electrically writable and erasable memory cells, an addressing circuit for reading, writing and erasing the memory, and a control unit which makes the access to the memory dependent on a validation operation with data comparison between stored reference data and code data entered from the outside, wherein the control unit, consisting of at least one comparator (57) for delivering a comparison signal (DOK), of a write control unit (3) for alternatively writing on a first or second operating data region which can be selected via an addressing unit depending on the comparison signal in such a manner that in the event of equality of the data, the first, and in the event of inequality of the data, the second operating data region is addressed, and having an erase control unit (9) for erasing the operating data regions, depending on the preceding execution of a write operation in the first operating data region.</p> |
