| 摘要 |
PURPOSE:To enable real time processing by changing each port of common memory for transfer having plural ports provided with write-only memories and read-only memories to access mode and copy mode. CONSTITUTION:A memory for transfer consists of four memories 21a-21d of the same memory capacity. Memories 21a, 21c are write-only memories that write data from a processor 11, and memories 21b, 21d are read-only memories that read data to a processor 12. A port 21A and B port 21B are changed periodically and alternately to access mode and copy mode by a switching signal generated by a mode switching signal generating circuit 53, and the mode in the A port 21A and B port 21B become reverse. Similarly, A port and B port of the memory for transfer 22 are changed to access mode and copy mode alternately. |
