| 摘要 |
PURPOSE:To utilize effectively a memory element, by preparing plural tracer memory groups of a narrow bit width and small capacity and connecting then in parallel or in series depending on the condition. CONSTITUTION:A data processing circuit is composed of tracer memories 1 and 2, a selection indicating circuit 3, an NOT circuit 4, an address register 6, an adder circuit 7, an AND circuit 8, a tracer memory change-over controlling FF circuit 9, OR circuits 5, 10, and 11, a multiple selection circuit 12, etc. The tracer memory change-over control FF circuit 9 is controlled by the overflow signal of the address register 6 and generates the write enable signal of the tracer memories 1 and 2. The tracer memories 1 and 2 are connected in parallel or in series by means of the output of the OR circuits 10 and 11, into which the write enable signal and a signal indicating the tracer bit width are inputted. |
