| 摘要 |
<p>A buffer-storage control system used in a pipeline data processor comprises a memory system having a two-level hierarchical structure composed of a main storage (3, Figure 1) and a buffer storage (8). The buffer storage (8) has a tag portion (21) and a data portion (22), each portion being composed of a plurality of ways. In the buffer-storage control sytem, the tag portion (21) and the data portion (22) can be independently accessed and the data portion (22) is so constituted for every way that it is possible to select one of a plurality of address passes and to select an address for a read access and an address for a write access for every way, thereby simultaneously effecting a read operation and write operation in the same machine cycle and executing the read access again only when the read access and the write access are effected for the same way.</p> |
