| 摘要 |
PURPOSE:To attain digital circuit integration of a frequency comparator circuit by comparing an output signal of a latch means and plural pulse signals delayed from the said signal so as to generate a discriminating signal for frequency comparison in response to the degree of coincidence of logical levels. CONSTITUTION:Pulse signals having frequencies f1, f2 are applied simultaneously to terminals T1, T2 of the latch means 3 and terminals T1, T2 of a comparator means 4. Signals having logically different levels depending on the difference between the frequencies of the pulse signals applied to input terminals 1, 2 are outputted to the output side of the latch means 3 and applied to a terminal T3 of the comparator means 4. The comparator means 4 compares a signal at the terminal T3 with an existing pulse signal (signal delayed substantially by one clock) applied to the terminals T1, T2, and when both signals are logically the same, a discriminating signal representing f1>f2 is outputted and when both signals are not the same, a discriminating signal representing f1<f2 is outputted. |
