| 摘要 |
An analog signal representing the measured output of a condition responsive transducer is supplied to a dual slope integrating analog-to-digital converter also receiving a regulated constant reference signal. Using the integrator in a non-inverting mode, the A/D converter operates in a single conversion cycle by first positively integrating a value of analog signal below a maximum negative input voltage for a fixed time period and then negatively integrating a voltage signal corresponding to the differential between the reference voltage signal and the maximum voltage for a variable time period to a comparative threshold. During integration, digital counts proportional to the variable integration period are accumulated and emitted for operating a digital device such as a digital display. Digital linearization of the converter output can optionally be provided by use of a programmed microcomputer reading a programmable-read-only-memory (PROM) to run a variable frequency clock. The clock is regulated to effect a frist phase converter time corresponding with an even multiple of the power line frequency.
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