| 摘要 |
A specialized processor capable of computing a sum of products S= SIGMA +/-Pi where every product Pi is the product of two n-bit complex operands Ai+j Bi, the multiplier, and Ci+j Di, the multiplicand, where j= 2ROOT -1. The processor includes an instruction storage, means for decoding instructions read out of said storage and for controlling the operation of the processor, a data storage, and a multiplication and accumulation unit which has two multiplier-accumulator devices and several buffers for storing the operands Ai, Bi, Ci and Di sequentially read out of data storage. The real part Ai and the imaginary part Bi of the multiplier are respectively applied to the Multiplier inputs of the multiplier-accumulator devices and the real part Ci of the multiplicand is applied to the Multiplicand inputs of the multiplier-accumulator devices, which simultaneously compute the products Ai Ci and Bi Ci. The imaginary part Di of the multiplicand is then applied to the Multiplicand inputs of the multiplier-accumulator devices. The first of these then computes the product Bi Di and adds the same to the product Ai Ci, while the second device computes the product Ai Di and adds the same to the product Bi Ci to simultaneously provide the real and imaginary parts of the product Pi. |
