| 摘要 |
PURPOSE:To speed up processing for an access request to a cache memory by providing an access waiting buffer and controlling selection access of a cache memory and a main memory according to the state of storing of a main memory access request. CONSTITUTION:When requested data are not in a cache memory 34, a main memory is accessed by an access request address written in an access waiting buffer 31 through a controlling circuit 35 that responds to mishit caused by a directory 33. Information of a block corresponding to this address is transferred to the cache memory 34, and when it hits, a recycle flag of the memory 31 is inverted through the circuit 35. At the same time, a reading pointer RP is made +1, and the memory 31 is emptied before completion of transfer of all information of one block through a controlling circuit 36. In the case of continued mishit, the memory 31 is emptied simultaneously with completion of transfer of all information of one block. Accordingly, access processing to the cache memory is made at a higher speed compared with the case where hit judgement is made after transferring of one block data. |
