| 摘要 |
PURPOSE:To obtain a fail-safe lower priority circuit by constituting each stage with a latch circuit and a pulse converting circuit, constituting a low-order output by the pulse converting circuit of the next stage and also using an AC pulse signal as an input signal. CONSTITUTION:Outputs Q2'-Qi' go to ''H'' level, because most of Qi goes to ''L'' level in the presence of an AC pulse input signal S1 and this level specifies a signal Di from an output signal D1 (signals at the terminal D is D1-Di in the order of low level) at the other terminal D, resulting that a pulse f0 becomes a DC of ''L'' level. When the input signal S1 does not exist but a signal S2 exists, the output Q1' goes to ''H'' level and enters a terminal D2 of an FF17b, and an output having the same frequency as a pulse f2 and opposite phase is given. Since this output specifies a signal D3 and thereafter, the output Q3' and thereafter go to ''H'' level and the f2 is outputted as the pulse f0. When an AND gate 19 of lower priority is defective, even if the input signals S1, S2 are given, outputs Q2' Q3' are pulse outputs of fail safe and the frequency of the pulse f0 is decreased remarkably. Thus, the lower priority of fail safe is attained in this way. |
