发明名称 |
CONSTRAINED PLACEMENT OF CONNECTED ELEMENTS |
摘要 |
An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated. |
申请公布号 |
EP3030991(A1) |
申请公布日期 |
2016.06.15 |
申请号 |
EP20140833873 |
申请日期 |
2014.08.06 |
申请人 |
ESS TECHNOLOGY, INC. |
发明人 |
BLAIR, ROBERT, L.;RISLER, DANIEL, A.;MALLINSON, A., MARTIN |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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