发明名称 RECEPTION LOGIC PROCESSING CIRCUIT
摘要 PURPOSE:To provide the same processing function as that of a conventional circuit with simpler circuit constitution than that of the conventional reception logic processing circuit by providing a temporary storage circuit delaying and outputting a multiplex input signal by one frame time and feeding back the output of the temporary storage circuit to a data selection circuit. CONSTITUTION:An error detection control circuit 5 checks the presence of an error at the 1st stage of the time section of each channel of an input signal and a data selection circuit 2 selects a signal at the 1st input terminal (a) and gives an output to the temporary storage circuit 3 when no error exists, and sends a control signal commanding that a signal at the 2nd input terminal (b), that is, a signal without error of the same channel before one frame time is selected and outputted when any error exists. Thus, if any error takes place on either channel, a signal without any error before one frame time is sent again. If an error takes place consecutively over 2 frames as to a channel, the signal of the frame just before the occurrence of the error is sent repetitively and circulatingly from a feedback circuit 4.
申请公布号 JPS6221373(A) 申请公布日期 1987.01.29
申请号 JP19850161014 申请日期 1985.07.20
申请人 NEC CORP 发明人 TERUI KOKI
分类号 H04N5/00;H04N5/60;H04N7/06;H04N7/08;H04N7/081 主分类号 H04N5/00
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