发明名称 |
Integrated memory circuit of a series-parallel-series type. |
摘要 |
<p>In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information which is provided by means of pulse duration variation. For adapting the time delay of the memory circuit (Figure 1).</p> |
申请公布号 |
EP0124942(A1) |
申请公布日期 |
1984.11.14 |
申请号 |
EP19840200629 |
申请日期 |
1984.05.03 |
申请人 |
N.V. PHILIPS' GLOEILAMPENFABRIEKEN |
发明人 |
PELGROM, MARCELLINUS J.M.;RAVEN, JOHANNES GERARDUS;SLOTBOOM, JAN WILLEM;HARWIG, HENDRIK ANNE;ANNEGARN, MARCELLINUS J.J.C. |
分类号 |
H04N5/907;G11C5/06;G11C7/00;G11C7/22;G11C8/18;G11C11/401;G11C19/28;(IPC1-7):11C19/28;11C5/06 |
主分类号 |
H04N5/907 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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