Wafer-level die to package and die to die interconnects suspended over integrated heat sinks

摘要

An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

主权项

1. A method of making an interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent said chips, with an electrically conductive heat sink disposed between said pads, the chips, electrically conductive heat sink and the packaging material forming a wafer, the method comprising:
spin coating a photoresist and patterning the photoresist on the wafer; reflowing the patterned photoresist on the wafer between at least two pads and over the electrically conductive heat sink; and applying and patterning a layer of metal on said wafer so that the layer of metal ohmically connects said pads and bridges over the photoresist.