| 摘要 |
<p>PURPOSE:To prevent the breakdown of the contents of a data holding RAM by repeating the level interruption processing until the start time point of a reset interruption or a time point when the power supply voltage is reset to the reference voltage. CONSTITUTION:The output of a voltage detecting circuit CMP2 is supplied to a level interruption terminal IRQ. The supply voltage VCC has a monotonous drop when it has a short break, and the level of the VCC is reduced less than the reference voltage REF2 of the COMP2. The level interruption of the IRQ is repeated before the VCC is reduced down to the reference voltage REF1 of a comparator CMP1. Then the resetting is always carried out to a main flow at the end of each processing. As a result, a normal operation is possible as long as the VCC is higher than the REF2 and without a level monitor. In such a way, it is avoided that a reset interruption is applied during execution of an instruction by applying a level interruption before a reset interruption. This prevents the breakdown of the RAM contents.</p> |
