| 摘要 |
<p>PURPOSE:To prevent the breakdown of a data holding RAM by having a connection so as to supply the output of a voltage detecting circuit to another program interruption terminal and delaying the start time point of a reset interruption until the processing period of another program interruption. CONSTITUTION:A delay circuit DLY is added to the input stage of a reset terminall RST of a CPU and has a delay time of several mus or more. The voltage of a voltage detecting circuit CMP2 is applied to an NMi terminal of the CPU as well as to the terminal RST through an input port and the circuit DLY. Thus an interruption is applied to the terminal NMi when the supply voltage VCC is reduced down to the reference voltage REF2 of a comparator CMP2. Then an interruption is applied to the terminal RST after several mus. Then the setting is always applied even though the VCC obtained after several mus is not reduced down to a level equivalent to the reference level REF1. This prevents the breakdown of the contents of a data holding RAM.</p> |
