Unit for prioritizing earlier and later arriving input requests

摘要

An interface unit is capable of interfacing a plurality of microprocessor units to a limited number of input/output devices or of interfacing a single microprocessor to a plurality of input/output devices. The interface unit uses a transparent latch to receive the input request. The output of the transparent latch is coupled to an encoder which provides an output to a decoder. The input requests are also coupled to a second encoder which provides an output to a comparator. The comparator compares the outputs between the encoders to determine if a subsequent request of a higher priority is received. If a subsequent request is of a higher priority than the present request being processed the present user will be overruled. One of the main features of the present invention is that the interface unit can operate in an asynchronous mode at a relatively high operating speed.