发明名称 GATE CIRCUIT DIAGNOSIS SYSTEM
摘要 PURPOSE:To detect immediately a faulty gate circuit by providing a counter within a device to be tested to count the shift number of clocks and referring to the count number from the count starting time point in a test mode. CONSTITUTION:A counter 11 exclusive for fault check is incorporated into a device 1 to be tested, and the count value of the counter 11 is displayed. This counter 11 is updated with the scan clock and receives +1 every time FF trains 1-1-1-N are shifted by a bit. Then the counter 11 is reset as soon as the FF train is reset, and the count value is set so as to have the complete coincidence with the FF train. As a result, a faulty FF can be immediately detected from the count value of the counter 11.
申请公布号 JPS59200353(A) 申请公布日期 1984.11.13
申请号 JP19830073405 申请日期 1983.04.26
申请人 FUJITSU KK 发明人 SHIOYA KATSUHIKO
分类号 G01R31/28;G01R31/3185;G06F11/22 主分类号 G01R31/28
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