| 摘要 |
PURPOSE:To simplify the constitution of a titled transceiver by using an oscillated output of a PLL circuit used for clock regeneration at the receiving side in common for a data clock at the transmission side. CONSTITUTION:This transceiver consists of a transmission/reception antenna 10A, a receiver 20A and a transmitter 30A. A signal received by the antenna 10A is demodulated through a high frequency circuit 21A and an intermediate frequency circuit 22A and fed to a D FF24A. A square circuit 25A and a PLL circuit 26A form a clock signal from a demodulation signal and an output from a frequency divider 26A4 in the PLL circuit 26A is fed to the D FF24A as a clock. An output from the frequency divider 26A4 is fed also to an encoder 32A of the transmitter 30A, where the transmission data is encoded. After the coded signal is modulated by an FSK modulator 33A, the signal is amplified by a power amplifier circuit 3A and fed to the other transceivers from the antenna 10A. |
