| 摘要 |
PURPOSE:To smoothly perform real time processing, by distributing the data transfer time by controlling a block transfer request signal to a receiving side processor so that the signal is generated at a fixed cycle. CONSTITUTION:The 1st block transfer request signal TRQ1 which indicates that 1-block quantity of data which can be transferred by a transmitting side processor 1 to a receiving side processor is ready, is generated to a control line 2 from the processor 1. By means of a timer 4, the processor 1 can set a transfer cycle time under a programmable condition. The timer 4 also generates a timer complete signal TCE and the timer complete signal is inhibited by an AND gate 6. The 2nd block transfer request signal TRQ2 is periodically produced by the timer 4. From the block transfer request signals TRQ1 and TRQ2, a block transfer request signal TRQ to the receiving side processor is sent from an AND gate 10. Therefore, the signal TRQ to the receiving side processor is periodically generated. |
