发明名称 PHASE LOCKED CIRCUIT
摘要 PURPOSE:To attain quickly the initial phase locking by using a complex conjugation value of two signals in a base band as the correction of the initial phase difference, and feeding back the product of two output signals of a complex multiplier as the input of a phase locked loop. CONSTITUTION:An AM-PM-VSB signal is branched into two, and applied to multipliers 11, 12, where the products f1, f2 between the signals and two orthogonal carrier waves having the same frequency as the carrier frequency are obtained respectively. The signals are converted into two orthogonal base band signals via a low pass filter 13. The signals are doubled by multipliers 14, 15 into signals g1(t) and g2(t) and added to a complex multiplier 17. An output of the 1st integration device 19 is applied to a correction vector forming section 20. This output is added to a vector correcting section 21 and the internal phase of this time is decided by multiplying a correction vector to the preceding value of the 2nd integration device 23 in terms of complex number. A vector AGC section 22 controls the gain so that the internal phase vector is traced on the unit circle.
申请公布号 JPS59198052(A) 申请公布日期 1984.11.09
申请号 JP19830072201 申请日期 1983.04.26
申请人 FUJITSU KK 发明人 TANIGUCHI TOMOHIKO;UMIGAMI SHIGEYUKI
分类号 H04L27/06 主分类号 H04L27/06
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