发明名称 SUBCHANNEL CONTROLLING SYSTEM
摘要 PURPOSE:To reduce the number of frequencies of subchannel code loading in the course of input/output processing of multiplexing operation and improve the throughput, by installing a subchannel updating bit, an old I/O address register, etc., to the data channel device of a data processing system. CONSTITUTION:A local storage 21, arithmetic device 23, multiprocessor, etc., are installed to the CPU2 of a data processing system. Moreover, a multiprocessor 34, controlling registers 311-316, subchannel updating bit 32, and old I/O address register 33 are installed to a data channel device 3 connected to the CPU2. When only subchannel information accumulated in the subchannel device 3 is updated, the bit 32 is turned on and the subchannel storing is executed. In case where the next input/output processing from an input/output interface 35 exists, subchannel loading is performed only when the machine number of the input/ output device coincides with the machine number of a previously processing device and, at the same time, the bit 32 is off. Thus the throughput is improved.
申请公布号 JPS59197921(A) 申请公布日期 1984.11.09
申请号 JP19830072457 申请日期 1983.04.25
申请人 FUJITSU KK 发明人 SUZUKI OSAMU
分类号 G06F13/12;G06F3/00 主分类号 G06F13/12
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