| 摘要 |
PURPOSE:To decode a code data with a simple logical circuit by providing a means inverting the output of the 1st count means when the output is coincident with the code data and the 2nd count means in synchronizing with the 1st count means. CONSTITUTION:A latch circuit 31 latches a code data in which a part of a data to be coded being consecutive of 0s or 1s is coded depending on the number of consecutive bits. When said code data is latched to the latch circuit, the 1st counter 33 starts counting from the initial value and when the output is coincident with said code data, a coincidence pulse is outputted from a comparator circuit 32. An output of a parallel control 34 is inverted when this pulse os outputted. The 2nd counter 35 counts a prescribed value in synchronizing with the output of the counter 33. A serial/parallel converting means 36 reads said inverted output in synchronizing with the operation of a counter 35. When the coincidence pulse is outputted from the comparator circuit 32, the operation of the counter is stopped. |
