Memory-based digital word sequence recognizer.

摘要

A circuit for detecting the presence of a digital information word sequence within a stream of digital information words comprises a memory (34, 36) which is subdivided into memory levels (A6-A9), each memory level having a plurality of memory locations (A0-A5). In a preferred embodiment, each memory level corresponds to the position of a word in the word sequence and the memory locations store a recognition status word corresponding to the bit pattern or patterns sought to be detected. The memory architecture of the present invention facilitates the detection of long sequences of digital words with the use of relatively few memory devices.