| 摘要 |
PURPOSE:To prevent erroneous communication by reporting a bus error to a central control part and resetting only a line control part if the bus error is detected during the direct memory access transfer between the line control part and a main storage part. CONSTITUTION:In case of reception of data from a line, receiving data is transferred from a line control part 3-i to a main storage part 2 through a bus 4 by direct memory access (DMA). At this time, a parity bit is generated by a bus error detecting circuit 8-2 and is added to receiving data and is transferred on the bus 4, and a parity error is detected by a bus error detecting circuit 8-1. When the error is detected by the circuit 8-1, a bus error signal 9 is outputted, and simultaneously, a line control part reset signal 11-i resultant from AND between this signal and a bus use right assigning signal 7-i is outputted, and only the control part 3-i is reset. A bus error reporting signal 10 is outputted to a central control part 1. Thus, since the line control part is reset before the end of transfer if the bus error is generated during DMA transfer, erroneous communication is prevented. |
