MOS transistor-based power buffer element with low response time and low consumption

摘要

The invention relates to power buffer elements produced with MOS transistors and having a low response time and low consumption. The power buffer element includes a conventional output stage including two oversize transistors T1 and T2. The transistor T2 has its gate controlled by the input binary element E. The transistor T1 has its gate controlled by the complement E of this input element. This complement E is obtained via a fast inverter device making it possible to limit the transient consumption, due to the passing from a logic input E = 0 to a logic input E = 1, and to increase the speed of the unit. For a logic level E = 0, the consumption of the inverter device T3, T4 is nil. The invention applies to power buffer elements produced as MOS integrated circuits. <IMAGE>