| 摘要 |
PURPOSE:To make it possible to extend a pulse signal by a counter from an integer value range to a real number value region, by providing an N-number pulse generator or a 1/N frequency divider. CONSTITUTION:An adder/subtractor 2 receives the frequency difference C of a frequency difference detector 1 and performs addition or subtraction from the polarity thereof. A return pulse generator 3 receives the count value C of the adder subtractor 2 to generate a return pulse signal line. The input pulse signal of the frequency difference detector 1 is added through an N-number pulse line generator 130 and a return pulse signal FB is transmitted to the difference input of an up-and-down counter through an N-bit register. The frequency difference detector 1, the adder subtractor 2 and the return pulse generator 3 are similarily constituted as conventional ones but the N-number pulse line generator 130 is added to the sum input of the frequency difference detector 1 and the N-bit register is added to difference input of the up-and-down counter while both of them respectively apply actions on an input pulse signal F1 or the return pulse signal FB.
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