| 摘要 |
<p>PURPOSE:To speed up an operation by providing an MOSFET for equalizing which is made to on state by the non-selective level of a selection signal supplied to a column switch MOSFET that connects a complementary data line to a common complementary data line. CONSTITUTION:When the complementary data lines of MOSFETs Q16, Q17 are made to the non-selective state by the supply of data line selection signals Y0, Y1 corresponding to the gates, Q16, Q17 are made to on state which corresponding column switches MOSFET Q12, Q13 and Q14, Q15 are made to off state, and equalizing is executed making complementary data lines D0, the inverse of D0 and D1, the inverse of D1 short-circuited state. Consequently, in the chip selection state to which address signals AX, AY are supplied, the level of complementary data lines D, the inverse of D connected to a memory cell according to actual selection timing of the memory cell, changes from level equal to each other according to memory information of the memory cell in case of reading operation, and changes according to writing signals in case of writing operation. Accordingly, the speeding up of the operation becomes possible.</p> |
