| 摘要 |
PURPOSE:To reduce the contact wear of a path selection relay PSR and to increase the PSR lifetime by using a logical circuit which prevents the drive of each PSR in the 2nd-4th switches to which no operation is needed when the release order of the 1st switch is executed. CONSTITUTION:In order to avoid the useless PSR drive, orders (O2, O1 and O0) are impressed to an NAND gate in a path selection drive control circuit 45 in addition to command information 40-42 for drive of path selection relays designated by the 2nd-4th switches. That is, in the case of the 1st switch release order of (O2, O1 and O0)=(0, 1 and 0), the logic of the NAND gate is set so that the outputs 50-52 of an AND gate corresponding to the information 40-42 are set at logic 0. Thus the drive is inhibited for the PSR of the 2nd-4th switches. As a result, the PSR in the 2nd-4th switches are never driven as long as the orders are applied. |
