| 摘要 |
PURPOSE:To reduce gate capacity and to attain a high-speed operation for an NOR circuit using an FET by using a gate electrode to which an input signal is supplied in a cut-off state or in a pentode area. CONSTITUTION:When the logical signals supplied to terminals 24-26 are all set at low levels, the potential of a circuit contact 50 is set at a low level and undergoes a level conversion through a level shifter 27. This level converted potential appears at a contact 51 and is delivered after the inversion of logical level carried out by an inverter 29. When the value obtained by subtracting the gate threshold voltage VT of each FET from the high level VIH of the logical input signal voltage is lower than the voltage VDD of a terminal 11, each FET has a pentode action. Therefore, the gate capacity is greatly reduced compared with a triode area. As a result, the capacitive load of a driving circuit which supplies the logical signal to such an NOR circuit is reduced. Thus the NOR circuit can be driven at a high speed and with small power consumption. |
