发明名称 RESET PROCESSING CIRCUIT
摘要 <p>PURPOSE:To reduce a processing at the time of a reinput by storing a reset condition of a stored data in a storage area of an RAM centering an MPU (microprocessor), and saving an optional data by its condition. CONSTITUTION:When a power source +5V is turned on, a reset signal is generated 6, and when a manual switch SW8 is turned on, the reset signal is inputted to an MPU1. As for an FF9, a terminal S attains to 5V immediately, but a terminal R is delayed by R1XC1 and goes to 5V, and a terminal Q of a level L goes to level H by the first pulse of the SW8 and continue its state. An area F of an RAM3 inhibits a reset by the manual SW8. When some reset signal is inputted, an ROM2 is started, a decoder 10 is turned on, a three-state buffer 11 is opened, an the output from the terminal Q is checked, and at the time of L, it is decided that the power source is turned on, the whole RAM is cleared, and at the time of H, it is cleared in leaving the area F. In such a way, the work for a reinputting after a reset is eliminated.</p>
申请公布号 JPS59189423(A) 申请公布日期 1984.10.27
申请号 JP19830063586 申请日期 1983.04.13
申请人 HITACHI SEISAKUSHO KK 发明人 HARA SHIYUUICHI
分类号 G06F1/24;G06F1/00 主分类号 G06F1/24
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