| 摘要 |
PURPOSE:To improve the performance of the titled device by improving the critical rate of rise of off-state voltage and critical peak off-state voltage of a thyristor without increasing the gate trigger current by a method wherein the depth of an N type emitter layer is formed small in tge periphery and large at the other part. CONSTITUTION:Said device including a thyristor chip is composed of four layers of an N<+> emitter layer 1, a P-base layer 2, an N-base layer 3, and a P-emitter layer 4. The depth x2 in the periphery of the emitter layer 1 of this device is formed smaller than the depth x1 of the other part. Even when the spacial charge layer of the P-N junction 10 expands, the reach of charges to the emitter layer 1 is prevented, thus improving the critical rate of rise of off-state voltage and critical peak off-state voltage characteristic of the thyristor, resulting in the improvement of the performance of said device. |
