| 摘要 |
PURPOSE:To improve the processing capacity of a macroinstruction with the minimum hardware quantity by using an arithmetic unit which can perform a normal operation with 2-word width and executing simultaneously both generation of a real address and check for segment size in a real address calculation mode. CONSTITUTION:In a real address calculation mode, the segment address which is extracted from a segment information register group 2 with the upper word of the arithmetic unit 4 is added with the upper byte of the offset address which is set to an instruction register 1. Thus the upper 16 bits of the real address are produced. At the same time, the matching information containing the segment size and the operand size set at a position (c) on a 16-bit bus 10 is added with the offset address of the register 1 set at a position (d) on the bus 10 at the lower word side of the operator 4. If a carry arises in this addition of lower words, the offset address of the operand exceeds the segment size.
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